Shallow trench isolation (STI) is a technique used for isolating active devices on a silicon substrate. This technique has been successfully used in both high performance logic chips as well as memory (e.g., DRAM and SRAM) chips. As the density of the transistors continues to increase, the amount of space separating the active devices decreases, causing the aspect ratio of the shallow trench to increase (i.e., the depth of the trench/the width of the trench becomes greater). With this increase in aspect ratio, it becomes more difficult to fill the shallow trench with an insulator (e.g., silicon dioxide) in such a way that there are no voids or seams in the insulating layer, and to produce a fully planarized surface at the completion of the STI process.
Various process sequences to form a shallow trench, isolation are described in "Silicon Processing for the VLSI Era," Vol. 3, by S. Wolf, Lattice Press, Sunset Beach, Calif., pp. 367-413. All of these techniques rely on the deposition of a dielectric film and various planarization techniques (e.g., chemical mechanical polishing, RIE etch back, etc.) to generate the isolation structure.
Memory capacities of Very Large Scale Integrations represented by DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and so on, have been increasing to be four times as large every three years. The DRAMs mainly manufactured at present are 64 Mb to 256 Mb. DRAMs of 1 Gb and 4 Gb which will be mainly manufactured in the near future are being studied. It is easily forecasted that DRAMs will progress to have memory capacities of 16 Gb, and then, of 64 Gb.
Such increases in the packing density in a limited chip area have been realized by reduction in size of semiconductor devices consisting of a circuit or circuits. For example, the minimum size of MOS transistors used for a 1 Mb DRAM is about 1 .mu.m, while the size will decrease significantly for 1 Gb DRAM. In addition to the reduced size of semiconductor devices, isolation regions positioned between the semiconductor devices on a chip are also related to the realization of the increase in the packing density. Specifically, a reduction of the isolation regions is indispensable to the increase in the packing density, and an isolation width comes to be required to be very small at 1 Gb DRAM generation.
Generally, the isolation regions are constructed of silicon dioxide which can be formed in the following way by a selective oxidation method. Unmasked portions of a silicon nitride film covering a silicon substrate are etched away, and then an exposed surface of the silicon substrate is selectively oxidated to form the silicon oxide which serves as an insulator.
This selective oxidation method, however, has revealed the following problems as the semiconductor device regions and the isolation regions therebetween decrease. First, the oxidation of the silicon substrate during the selective oxidation process progresses even to regions covered with the silicon nitride film, and as a result, a silicon dioxide film called a bird's beak spreads. Therefore, there is a limit in the reduction of the isolation regions. Second, a long oxidation process time is required. Because of this, the silicon substrate suffers from stresses and is flawed. As a result, characteristics of the semiconductor devices fabricated on the substrate deteriorate.
A trench-filling-up isolation method has been proposed as an alternative method of the selective oxidation method to solve the above mentioned problems. This method consists of forming rectangular trenches in a silicon substrate and filling the trenches up with a silicon oxide layer or other layers. According to this method, only the trench regions serve as isolators. Therefore, the reduction of the isolation regions is possible. In addition, because this method has no thermal process over a long time, deterioration in the substrate characteristics is prevented.
The trench-filling-up method is an isolation method suitable for the fabrication of semiconductor integrated circuits of high packing density. However, this method has the following problems.
FIG. 1 is a schematic sectional view showing an isolation region formed by the above described conventional trench-filling-up method. In FIG. 1, a reference numeral 20 designates a silicon substrate on which a trench 21 is formed by a reactive ion etching (RIE) method. A reference numeral 22 is a silicon dioxide layer which fills up the trench 21. The silicon oxide layer 22 is first grown by a CVD (Chemical Vapor Deposition) method and then processed to lead to the state as shown in FIG. 1. Disadvantageously, a very small ditch or void 23 is generated on the surface of the silicon dioxide layer in the trench 21 for the following reason. The silicon dioxide layer 22 for filling up the trench 21 grows not only on the bottom of the trench 21 but also on the sides thereof and at almost the same speed. Accordingly, in such a narrow trench as has a width "a" and a depth "b", the silicon dioxide layer 22 growing from the opposite sides of the trench 21 collide with each other in the middle of the trench 21 and a junction 24 is formed to a predetermined depth. The union of the silicon oxide layer 22 at the junction 24 is so weak that the silicon dioxide is easily etched along the junction 24 during a rinse process using a dilute hydrofluoric acid which is an indispensable process in the silicon semiconductor fabrication process, thus the small ditch generates.
Generally, formation of a gate insulator film and metallization for a gate electrode wiring for a MOS transistor follow the formation of the isolation regions. At this time, if small ditches exist in the isolation regions, cutting of the wiring takes place. In addition, if wiring materials remain in the small ditch, a short circuit takes place.
As the ratio of depth b to width a (also referred to as the aspect ratio) increases for both DRAMs and CMOS, it becomes more difficult to achieve within wafer and wafer-to-wafer uniformity and reproducibility in the filling process. As explained above, the filling process produces voids along the center of the trench, and these voids impose reliability problems during subsequent etching processes as well as areas of stress concentration which impact the lifetime of the device. What is needed is an improved filling process for trench isolations having aspect ratios greater than two.